Senior ASIC Design Engineer
Duty station:
San Jose
Job Description:
What We Offer
Opportunity to work on cutting-edge AI-SSD architecture
High-impact role in next-generation storage innovation
Collaborative and fast-paced engineering culture
Responsibilities
Contribute to the microarchitecture design of next-generation SSD controllers and storage subsystems, with a focus on optimizing architectures for AI applications.
Develop and write detailed design specifications, microarchitecture documents, and implementation guidelines.
Design and implement key functional blocks using Verilog/System Verilog RTL.
Work closely with the verification team to define test plans, coverage analysis, and support full-chip simulation, debug, and validation.
Collaborate with the physical design team to ensure timely and high-quality RTL-to-GDS implementation.
Support post-silicon bring-up, debugging, and performance validation in the lab.
Work closely with firmware and system teams to ensure feature alignment and product-level performance targets are met.
Perform design analysis and optimization to improve performance, power efficiency, and area (PPA).
Job Requirements:
Qualifications
Bachelor’s degree or above in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
3+ years of ASIC design experience, preferably in storage or high-performance SoC design.
Strong understanding of the full ASIC design flow, including both front-end and back-end processes.
Solid experience in digital design and RTL development, with proficiency in Verilog/System Verilog.
Familiarity with at least one scripting/programming language (e.g., Python, Tcl, Perl, Shell).
Strong problem-solving skills, self-motivated, and able to work effectively in a collaborative team environment.
Preferred Qualifications
Experience in SSD controller or storage system design.
Familiarity with AI/ML workload acceleration, memory/storage hierarchy, or data path optimization.
Hands-on experience with synthesis (Design Compiler), STA, CDC, lint, and formal verification flows.
Knowledge of UVM-based verification methodologies.
ASIC Design Engineer
Duty station:
San Jose
Job Description:
1. Contribute to micro-architecture designs for state-of-the-art high-speed low-power digital IPs.
2. Implement design modules using hardware description language (HDL).
3. Design schemes for multi-clock domain crossing and synchronization.
4. Drive OVM/UVM design verification and support FPGA engineers for early prototyping.
5. Execute RTL-to-GDS development flow, including synthesis, schematics design, and supervising custom layout.
6. Check timing closure, and analyze the performance/power/area of designed IPs.
7. Support IP integration to SoC, including soft-IP RTL integration and hard-IP GDS macro integration.
8. Perform post-layout Hspice simulation to characterize the designed circuit.
9. Assist with test program development, chip bring-up, validation, and production maturity.
Job Requirements:
1. Master’s degree in Electrical Engineering/Computer Science.
2. 6 months experience as an ASIC Design Engineer or Verification Design Engineer.
3. Proficient with Verilog, SystemVerilog, and Python or Perl.
4. Strong knowledge of micro-architecture design, function modeling, RTL coding, and SoC Integration.
5. Good at multi-clock domain designs, timing analysis, and optimization.
6. Experience in SystemVerilog OVM/UVM, synthesis, mixed-signal circuit schematics design, and layout design.
7. Able to proactively take on responsibilities and competent to work in a start-up environment.
