ShangHai
1. Create schematic with FPGA, network switch, PWM, LOD, inductor, and in-house ASIC by using CADENCE capture;
2. Work with PCB engineers for layout process such as stack-up, high-speed signal route strategy, board dimension, etc.;
3. Review PCB placement and layout; deliver the high-quality PCB board with CADENCE Allegro;
4. Check the source code for in-house ASIC design to synthesize the FPGA bit-file with clock constrains and PIN location, analyze timing if need, work with design team to fix the error and critical warnings, familiar with XILINX VIVADO or SYNOPSYS SYNPLIFY.
5. Insert the ILA (Internal Logic Analyzer) to capture the signal for the design team debugging.
6. Evaluate and exam the PCB board to ensure the resistor and capacitor are installed correctly; ensure power rail is not shorten to the GND.
7. Measure the power rail''s voltage and current to confirm the hardware board are functioning correctly; especially the power on/off sequence and clock.
8. Use SYNOPSYS HSPIC and IBIS-AMI module to measure waveform and eye diagram for high speed signal, such as PCIE, 10G-KR; run eye diagram simulation with PCB S-parameter.
Bachelor’s degree in Electrical Engineering/Applied Physics/Related;
24 months experience as a Hardware Engineer/FPGA Engineer.
ShangHai
Participate as a team member and work effectively inside and outside of the team;
Design a variety of advanced application specific integrated circuits (ASIC), including SSD controllers, using modern ASIC techniques;
Specify circuit architectures that will meet system-level requirements, and implement the architectures using hardware description language (HDL);
Characterize the performance of the designed circuit;
Integrate the design into system on Chip (SoC);
Analyze and debug simulation failures, as well as analyzing testing results and providing improvements after the SoC is manufactured.
Master’s degree in Electronics Engineering/Electrical Engineering;
6 months experience in the job offered.
ShangHai
Create independently leading edge constrained-random verification environments and use them to drive functional correctness of innovative SoCs.
Be responsible for a wide variety of advanced verification tasks, including designing self-checking test benches using modern verification techniques, such as Universal Verification Methodology (UVM).
Design verification components such as bus functional models, monitors, and behavioral models.
Implement functional coverage and assertions using System Verilog.
Develop testing and functional coverage plans based on device specifications.
Analyze and debug simulation failures, as well as functional coverage results.
Master’s degree in Electronics Engineering/Electrical Engineering;
6 months experience as a Verification Design Engineer or Electronics Engineer.
ShangHai
Create leading edge data path controllers.
Be responsible for a wide variety of advanced design tasks, including designing DDR controllers and data compression engines using modern ASIC techniques;
Specify circuit architectures that will meet system-level requirements, and implement the architectures using hardware description language (HDL), and build test cases to verify the correctness of the design;
Assist characterizing the performance of the designed circuit;
Work to integrate the design into our System on Chip (Soc);
Facilitate the debugging of firmware on data path controllers;
Analyze and debug simulation failures, as well as analyze test results and provide improvements after the SoC is manufactured.
Master’s degree in Computer Science/Computer Engineering/related;
6 months experience as a Logic Design Engineer or Digital Design Engineer.
ShangHai
Independently creating leading edge data path controllers, including controllers for error correction codes (ECC) and DDR.
Specify circuit architectures that will meet system-level requirements, and implement the architectures using hardware description language (HDL).
Independently create leading edge constrained-random verification environments and use them to drive functional correctness of designed blocks.
Be responsible for a wide variety of advanced verification tasks, including designing self-checking test benches using modern verification techniques, such as Universal Verification Methodology (UVM).
Develop testing and functional coverage plans based on device specifications.
Analyze and debug simulation failures, as well as functional coverage results.
Master’s degree in Electronics Engineering/Electrical Engineering;
6 months experience as an ASIC Design Engineer or Verification Design Engineer.
ShangHai
Design, implement and verify PCIe, SATA, and other functional blocks using Verilog/System Veri-log.
Evaluate micro architecture and RTL implementation tradeoffs and come up with final solutions to deliver design that meets target power, performance and area goals.
Prepare detailed document including function description, interface definition and verification plan.
Work with other engineers to perform chip level verification through FPGA and/or chip-level simulation/verification.
Work with physical implementation team to address synthesis, place & route, timing and DFT issues.
Help support chip bring-up in the lab.
Master’s degree in Electronics Engineering/Electrical Engineering;
6 months experience as a Digital IC Design Engineer or Staff Digital IC Design Engineer.
ShangHai
Develop high-performance low-power analog and mixed-signal integrated circuits for today''s highly sophisticated CMOS SOC products, using state-of-the-art deep sub-micron CMOS technologies.
Design high-performance analog-to-digital converters (ADCs), digital-to-analog converters (DACs), operational amplifiers, temperature sensors, bandgaps and regulators.
Design voltage controlled oscillators (VCOs), phase-frequency detectors (PFDs), phase-locked loops (PLLs) and delay-locked loops (DLLs).
Design filters, finite-impulse response (FIR) filters, and decision feedback equalizer (DFE).
Design high speed serializer-deserializer (SerDes) and timing circuits, including PLL and CDR.
Participate in circuit architecture, circuit implementation, design review, layout and silicon validation.
Master’s degree in Electronics Engineering/Electrical Engineering;
6 months experience as a Hardware Design Engineer or Hardware/RF Design Engineer.
ShangHai
Design, build, and benchmark distributed storage systems (e.g., Ceph and HDFS). Optimize distributed storage software stack on Innogrit hardware.
MS or above in Computer Science/Engineering or equivalent;
Experience in building scalable, high-performance, highly available distributed systems;
Experience in working with big data technologies such as Spark, Hadoop ecosystems, Kafka,
Zookeeper, Elasticsearch, Yarn, MapReduce, Storm, HBase and Cassandra;
Familiar with Linux operating system and its files system;
Familiar with Hadoop ecosystems and distributed file systems (HDFS, GFS, …);
Familiar with SQL and NoSQL database.
ShangHai
Layout, PCB design, system bringup and debugging in the lab.
MS in Electrical Engineering;
5+ years in designing boards and FPGA with Verilog;
Experience with Orcad/Allegro and layout supervision;
Good understanding of signal integrity and layout simulation tools like Hyperlynx or PowerSI;
System bringup and debug in lab. Usage of Oscilloscopes, Logic Analyzers and debug tools like Realview, Chipscope;
Self-driven and motivated to work in an active environment.
ShangHai
Optimize hardware for machine learning kernels and evaluate performance and power efficiency.
MS in Electrical Engineering;
3+ years of machine learning experience;
Strong understanding of state-of-the-art techniques such as deep neural networks;
Strong background in hardware architecture (pipelining, memory hierarchies, DRAM,power and area estimates) and mathematical;
Strong software skills in C++; Ability to deeply understand application needs and algorithms.
Additional Success Factors:
Experience with ARM or POWER ISA;
Ability to proactively take on responsibilities and competent to work in a start-up environment;
Ability to work with cross-functional teams.
ShangHai
Participate as a team member and work effectively inside and outside of the team.
Design a variety of advanced application specific integrated circuits (ASIC), using modern ASIC techniques.
Specify circuit architectures that will meet system-level requirements, and implement the architectures using hardware description language (HDL).
Characterize the performance of the designed circuit. Integrate the design into system on Chip (SoC)
Analyze and debug simulation failures, as well as analyzing testing results and providing improvements after the SoC is manufactured.
Master’s degree in Electronics Engineering/Electrical Engineering;
6 months experience as an ASIC Design Engineer.
ShangHai
Cover all aspects of digital SoC design, focusing on architecture, RTL, verification, logic synthesis, and timing analysis to deliver a design meeting power, performance and area goals.
BS and/or MS in Electrical Engineering;
12+ years of RTL design/architecture experience;
Proven record with the definition and development of complex SoCs;
Know both frontend and backend flows;
Strong knowledge of Verilog, System Verilog, Synthesis and Static Timing Analysis;
Self-motivated and able to work effectively both independently and in a team.
Additional Success Factors:
Experience with designing for ARM CPU based SoC;
Ability to proactively take on responsibilities and competent to work in a start-up environment;
Management experience.
ShangHai
Create leading edge constrained-random verification environments and drive functional correctness of SoCs.
MS in Computer Science with 6 month+ work experience;
Experience in ASIC/SoC verification with SV/UVM environments;
In-depth knowledge of verification flows,constrained random verification process,
functional coverage, code coverage, assertion methodology & philosophy;
Team player with excellent communication skills and the desire to take on diverse challenges.
Additional Success Factors:
Advanced knowledge of CPU & SoC architecture/design;
Experience in verifying data storage protocols such as SATA, PCIe, NVMe;
Knowledge of formal verification, hardware emulation.
ShangHai
Cover PCIe and other IP block designs, focusing on architecture, RTL, logic synthesis, and timing analysis to deliver design target goals.
BS/MS in Electrical Engineering;
12+ years of RTL design and/or architecture experience;
Expertise in PCIe standards including SR-IOV designs and PCIe Transaction Layer;
Experience in PCIe application layer implementation,PCI logic analyzers, PCIe components;
Know Verilog, System Verilog, Synthesis and Static Timing Analysis.
Additional Success Factors:
Ability to proactively take on responsibilities and competent to work in a start-up environment.
ShangHai
Cover error correction code designs and deliver design meeting target power, performance and area goals.
BS/MS in Electrical Engineering;
12+ years of ECC design and/or architecture experience;
Expertise in BCH, LDPC, and proven track record;
Knowledge of logic design principles along with timing and power implications;
Strong knowledge of Verilog, System Verilog, Synthesis and Static Timing Analysis.
Additional Success Factors:
Ability to proactively take on responsibilities and competent to work in a start-up environment.
ShangHai
Provide analog and mixed-signal circuits. Lead analog/mixed-signal design team to deliver designs goals.
BS/MS in Electrical Engineering;
10+ years of analog circuit design experience;
Experienced with both high and low speed interfaces like GPIOs, PCIe, NVMe, SAS, etc;
Proven track record of successful analog circuitry delivery for SoC integration;
Self-motivated and able to work effectively both independently and in a team.
Additional Success Factors:
Ability to proactively take on responsibilities and competent to work in a start-up environment;
Management experience.
ShangHai
Generate high quality deliverables to backend vendor. Establish milestones and goals to ensure schedule and quality.
BS/MS in Electrical Engineering;
Solid chip development experience;
10+ years of experience in place & route and physical design, including floor planning, static timing verification and layout verification;
Prior experience supervising team members and contractors;
Self-motivated and able to work effectively both independently and in a team.
Additional Success Factors:
Ability to proactively take on responsibilities and competent to work in a start-up environment.
ShangHai
Identify & define hardware accelerators along with all SoC design, deliver a design meeting target power, performance and area goals.
BS/MS in Electrical Engineering;
10+ years of RTL design and/or architecture experience;
Strong understanding of Compression (DEFLATE, LZS, Huffman Encoding, Dedup, etc.) or Crypto algorithms (symmetric & asymmetric key algorithms) or SSL/TLS protocol;
Strong knowledge of Verilog, System Verilog, Synthesis and Static Timing Analysis;
Self-motivated and able to work effectively both independently and in a team.
ShangHai
Design and implement drivers and libraries that communicate with our chip.
BS/MS in Computer Science;
5+ years experience writing device drivers for Linux;
Experience with networking or storage stacks;
Architectural sense;
Ability to write correct C or C++ code fast;
Experience with operating system bypass and zero-copy techniques, including RDMA;
Experience with PCIe Express single-root IO virtualization (SR-IOV).
ShangHai
Design and implement the infrastructure software.
BS/MS in Computer Science;
5+ years experience in firmware development;
Experience with embedded CPU (preferably ARM) and RTOS;
Experience in code generation;
Experience with regression and product-level testing;
Ability to write correct C or C++ code fast;
Experience in Python and its various libraries and tools;
Self motivated, independent and proactive.
Additional Success Factors:
Great communication and organizational skill to communicate with other developers about their requirements and keep track of them.
ShangHai
Innogrit is looking for an experienced Program Manager to join the sales and marketing organization. In this role, you will organize and coordinate internal programs and align with customer project schedules and ensure successful execution.
Responsibilities Include:
Be a leader and overseer of customer programs and delivery of products.
Develop and manage internal program schedules, milestones and deliverables and align with customer program schedules, milestones and deliverables
Work with and manage development schedules with multiple different internal engineering teams
Effectively and efficiently track tasks and close issues in a timely manner
Communicate to internal teams customer requirements
Communicate to customers program progress and preset customer expectations, translate internal processes and highlight issues in a meaningful and proactive manner
Establish processes
Understand, build, and track budgets to ensure budgets being met
Be the main program communication channel for executive management, sales and customers
5+ years of program/project management experience
Ability to handle multiple projects and customers
Strong communication ability
Experience with international customers
Experience with managing programs across multiple different time zones
Experience establishing processes and maintaining and managing those processes
Ability to dissect problems and make effective decisions
Ability to handle stressful situations and communications to customers
Outgoing personality with the ability to create strong relationships and trust
Fast learner with the ability to immediately be seen as a leader and “go to” person
Creative thinker
MSFT office (Excel, powerpoint, project, etc) a must
Knowledge of different Bug tracking tools
Bachelors degree