PCIe Integration Engineer
Duty station:
San Jose
Job Description:
Education and Experience
1.Educational Background:
1).Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
2.Professional Experience:
1).5+ years of experience in digital design and IP integration.
2).Strong experience in PCIe integration.
3).Strong knowledge of PCIe PHY, link, and transaction layers.
4).Experience with NVMe and CXL protocols and their integration in SoCs.
Job Requirements:
Technical Skills:
1.Hardware Design and Verification:
1).Proficiency in Verilog.
2).Experience with hardware verification languages and methodologies such as System Verilog, UVM (Universal Verification Methodology).
3).Knowledge of digital design principles, timing analysis, and signal integrity.
2.SoC Architecture and Design:
1).Understanding of SoC architecture, including memory hierarchy, bus systems, and peripheral integration.
2).Experience with high-speed serial interfaces, particularly PCIe (PCI Express).
3).Knowledge of NVMe (Non-Volatile Memory Express) and CXL (Compute Express Link) standards and protocols.
4).Familiar with performance optimization.
3.PCIe IP Integration:
1).Experience in integrating PCIe IP from vendors such as Synopsys, Rambus, or PLDA.
2).Familiarity with PCIe protocol, including its PHY and Link layers and transaction flow.
3).Understanding of PCIe PHY (Physical Layer) and its integration challenges.
4).Experience with handling and interpreting PCIe error messages for debugging and compliance.
Soft Skills:
1.Problem-Solving and Analytical Skills:
1)Strong analytical and problem-solving skills to debug complex design issues.
2.Collaboration and Communication:
1).Ability to work collaboratively in a team environment.
2).Good communication skills to effectively interact with cross-functional teams, including software, hardware, and systems engineers.
3.Documentation:
1).Ability to document design specifications, test plans, and validation reports clearly and comprehensively.
4.Continuous Learning:
1).Willingness to stay updated with the latest advancements in PCIe, NVMe, and CXL technologies and their applications.
ASIC Design Engineer
Duty station:
San Jose
Job Description:
1. Contribute to micro-architecture designs for state-of-the-art high-speed low-power digital IPs.
2. Implement design modules using hardware description language (HDL).
3. Design schemes for multi-clock domain crossing and synchronization.
4. Drive OVM/UVM design verification and support FPGA engineers for early prototyping.
5. Execute RTL-to-GDS development flow, including synthesis, schematics design, and supervising custom layout.
6. Check timing closure, and analyze the performance/power/area of designed IPs.
7. Support IP integration to SoC, including soft-IP RTL integration and hard-IP GDS macro integration.
8. Perform post-layout Hspice simulation to characterize the designed circuit.
9. Assist with test program development, chip bring-up, validation, and production maturity.
Job Requirements:
1. Master’s degree in Electrical Engineering/Computer Science.
2. 6 months experience as an ASIC Design Engineer or Verification Design Engineer.
3. Proficient with Verilog, SystemVerilog, and Python or Perl.
4. Strong knowledge of micro-architecture design, function modeling, RTL coding, and SoC Integration.
5. Good at multi-clock domain designs, timing analysis, and optimization.
6. Experience in SystemVerilog OVM/UVM, synthesis, mixed-signal circuit schematics design, and layout design.
7. Able to proactively take on responsibilities and competent to work in a start-up environment.
