数字IC设计工程师

职位描述:

  • 使用Verilog / System Veri-log设计,实现和验证PCIe,SATA和其他功能块。
  • 评估微架构和RTL实现权衡,并提出最终解决方案,以提供满足目标功耗,性能和面积目标的设计。
  • 准备详细的文件,包括功能描述,界面定义和验证计划。
  • 与其他工程师合作,通过FPGA和/或芯片级仿真/验证执行芯片级验证。
  • 与物理实施团队合作,解决综合,布局和路线,时间安排和DFT问题。
  • 帮助支持实验室中的芯片启动。

职位需要:

  • 电子工程/电气工程硕士学位;
  • 半年以上数字IC设计工程师或员工数字IC设计工程师的经验。

Firmware Engineer ( Shanghai, Chengdu )

职位描述:

Design and develop firmware for storage product.

ASIC validation, verify and testing storage product HW functions.

Design and develop firmware using software development best practices.

Cooperating Firmware testing, including optimization and debugging of HW/FW problems.

职位需要:

Master or Bachelor degree in CS/CE/EE or related engineering discipline.

Solid C programming experience in embedded system development is a must-have.

Knowledge in embedded systems and hands-on experiences in developing controller firmware.

Solid knowledge of industry standards including ARM CPU, SATA, and PCI-express, etc.

Knowledge of mass storage systems and device drivers is preferred.

Experience of storage firmware development is a plus.

oral and written communication skills in both English and Chinese.

System Test Engineer (Chengdu)

职位描述:

Design and develop system test plan and test scripts based on design documents.

Develop and maintain automation testing tools and test environment.

Find SSD bugs through grey and white box testing. Report and track bugs, follow up with FW team.

Analyze and resolve issues with the software, firmware and hardware team.

职位需要:

B.S. or above in CS/CE/EE or related engineering discipline.

Solid software program skill, experiences on C/C++ and script language, such as Python/Perl/Bash.

Solid knowledge of industry standards including SATA, NVME and PCI-express, etc.

Knowledge of mass storage systems, Flash memory(NAND) and device drivers is preferred.

Knowledge of SSD flash translation layer, wear leveling, garbage collection etc.

Knowledge in Jenkins is a plus.

Experience in SSD firmware development/test is a plus.

Good communication skills to coordinate with different teams, ability to communicate clear and precise information

ASIC Design Engineer/ASIC Algorithm Design and Implementation Engineer ( Shanghai )

职位描述:

Participate in architecture definition, implementation and verification phases of SSD chip development flow;

Micro-Architecture design and RTL (Verilog) coding for a variety of modules within SSD controller;

Help create detailed design specifications and test plans;

Work with cross-functional teams (hardware, software/Firmware, diagnostics) to deliver fully qualified products;

Algorithm study and investigation, provide the best scheme for algorithm implementation; Those algorithms are related to source encoding/decoding, channel encoding/decoding, or cryptographic services.

职位需要:

MS degree in EE/ME/CS or related fields;

Solid understanding about digital circuit design and implementation flow;

Familiar with industry standard protocols and interfaces such as ONFI/Toggle NAND interface, eMMC/UFS protocol, or AMBA protocol family;

Good coding style and be able to deliver accurate, concise, and clear design documents;

Understanding ASIC design flow, hands-on experience in using industrial standard EDA tools; Strong debug skills;

Self-motivation, teamwork and strong communication skills are essential;

Proficient in both written and verbal English;

Knowledge of UVM is a plus;

Being familiar with Error Correcting Code (such as Reed-Solomon Codes, BCH, or LDPC) is a plus.

ASIC Validation Sr. Engineer/Engineer ( Shanghai )

职位描述:

Design and develop firmware for storage product.

ASIC validation, verify and testing storage product HW functions.

Design and develop firmware using software development best practices.

Cooperating Firmware testing, including optimization and debugging of HW/FW problems.

职位需要:

Master or Bachelor degree in CS/CE/EE or related engineering discipline.

Solid C programming experience in embedded system development is a must-have.

Knowledge in embedded systems and hands-on experiences in developing controller firmware.

Solid knowledge of industry standards including ARM CPU, SATA, and PCI-express, etc.

Knowledge of mass storage systems and device drivers is preferred.

Experience of storage firmware development is a plus.

oral and written communication skills in both English and Chinese.

Design Verification Engineer ( Shanghai )

职位描述:

Create independently leading edge constrained-random verification environments and use them to drive functional correctness of innovative SoCs.

Be responsible for a wide variety of advanced verification tasks, including designing self-checking test benches using modern verification techniques, such as Universal Verification Methodology (UVM).

Design verification components such as bus functional models, monitors, and behavioral models.

Implement functional coverage and assertions using System Verilog.

Develop testing and functional coverage plans based on device specifications.

Analyze and debug simulation failures, as well as functional coverage results.

职位需要:

Master’s degree in EE/CS; 

3+ years in ASIC/SoC verification with UVM/SV environment.

In-depth knowledge of verification flows, constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy.

Experience is SSD controller is a big plus.

Physical Design Engineer

职位描述:

Looking for a talented and highly self-motivated candidate that has strong background and hands-on experience in the physical design for advanced technology nodes. The candidate will work on the physical implementation of our state-of-art SoC products. Driving all aspects from RTL to GDS including timing and physical trade-offs, die size reduction and delivery of final product on schedule while meeting design goals.

 

Responsibilities:

Perform physical implementation of the ASIC design from netlist to GDS, including floorplanning, power grid and clock network implementation, place and route, timing closure and physical verification.

Work with multiple teams on the SoC architecture study and timing/power/area design target.

Working with different IP owners to ensure seamless IP integration at full chip level.

Writing scripts for design automation flow and productivity enhancement.

 

Qualifications

Experience in ASIC Physical Design from netlist to GDSII.

Experience in using EDA tools such as Synopsys ICC or Cadence SOC Encounter

Hands on experience in Floorplanning, CTS, STA

Experience in Power grid, clock tree, and low-power flow implementation methods

Hands on experience with STA using Primetime, power analysis.

Hands on experience with IR drop analysis, formal verification and physical verification.

Timing closure, ECO process using PrimeTime

Programming and scripting skills (Tcl, perl ,shell)

DFT/DFM knowledge is a plus

Self-motivated and able to work effectively in a start-up environment

Ability to execute to stringent schedule & die size requirements and effective communication skills

 

工作职责:

负责芯片从网表到GDS的后端物理实现,包括布局规划,时钟树生成(CTS),布局布线,时序优化和收敛,以及GDS的物理验证

和多个设计团队合作制定芯片结构,参与制定芯片性能/面积/功耗等方面的设计目标,

与不同功能模块的设计团队合作保证功能模块的顺利集成。

优化后端设计自动化的流程和提高团队设计开发效率

 

任职要求

后端工作经验,微电子或者相关学科硕士以上学历、

良好的沟通能力和团队精神,能够在精干的团队环境里高效率的发挥自己的能力。

熟练使用主流P&R流程工具(Synopsys、Cadence的相关P&R工具)

具有从netlist到GDS整个流程的实际经验,包括布局规划,power gird,时钟树生成(CTS),布局布线设计,时序收敛,IR-drop,lvs/drc。

具备扎实的时序分析知识与signoff的技能。

具备DFT/DFM相关经验的优先。

熟练的脚本编写技能(Tcl,perl, shell)

职位需要: